Interphase Tech 4538 Manual de usuario

4538 PMC® T1/E1/J1 Communications ControllerHardware Reference ManualDocument No. UG4538-001$Print Date: 2FWREHU

Contentsiv Interphase CorporationIn Situ EPLD Programming

T1/E1/J1 Framer Initialization78 Interphase CorporationSEC/FSC ConfigurationThe SEC/FSC signal of the QuadFALC is connected to CPM and is used for the

Chapter 3: Programming the Peripherals4538 Hardware Reference Manual 79RCLK1 is one of the four channels’ internally-generated receive route clocks (R

T1/E1/J1 Framer Initialization80 Interphase CorporationRCLK1 Configuration as TDM bus clock8 KHz synchronization pulse generated by the internal DCO1-

Chapter 3: Programming the Peripherals4538 Hardware Reference Manual 81not go to a continuous level, but is the free running frequency of DCO-R. Since

T1/E1/J1 Framer Initialization82 Interphase CorporationFraming and Line Coding InitializationCommon InitializationT1 Specific InitializationE1/E1-CRC4

Chapter 3: Programming the Peripherals4538 Hardware Reference Manual 83E1 Non-CRC4 Specific InitializationE1-CRC4 Specific InitializationClock Synchro

The Ethernet Port Initialization84 Interphase CorporationTransmit Pulse ShapeFor each type of Line Build-Out (LBO), the shape of the transmit pulse mu

Chapter 3: Programming the Peripherals4538 Hardware Reference Manual 85For a simple SMC1 controller example in polling mode:See Boot Firmware: app\c\m

The TTY Framer Initialization86 Interphase Corporation

44538 Hardware Reference Manual 874Accessing the 4538 on the PCI SidePowerSpan Configuration by the PCI HostSeveral elements of the PowerSpan are auto

4538 Hardware Reference Manual vList of FiguresFigure 1-1. 4538 Structure...

Controlling the PCI-to-Local Interrupt88 Interphase CorporationFor a normal use, the card should be reset by the PCI host (if needed) using only the–S

Chapter 4: Accessing the 4538 on the PCI Side4538 Hardware Reference Manual 89Local to PCI Interrupt (–INTA)The PowerQUICC II can generate an interrup

Access to the FLASH EEPROM Through PCI90 Interphase CorporationWhen the processor is running, the PCI bus has access to all the elements connected to

Chapter 4: Accessing the 4538 on the PCI Side4538 Hardware Reference Manual 91Example 4-5. FLASH Read and Write Routines (From PCI Side)

Serial EEPROM Connected to the PowerSpan92 Interphase CorporationFLASH EEPROM Programming AlgorithmsThe boot memory is a 4Mx8 AMD 29LV033 FLASH device

Chapter 4: Accessing the 4538 on the PCI Side4538 Hardware Reference Manual 93In Situ EPLD ProgrammingGlue logic is implemented in some EPLDs that can

PCI Deadlock Situations94 Interphase CorporationExample: The PCI host sets the DMA buffer descriptors into the local memory, and then it runs the DMA

54538 Hardware Reference Manual 955Connectors and Front PanelConnector PlacementFigure 5-1. Connectors on the Component SideFigure 5-2. Connectors a

Front Panel96 Interphase CorporationFront PanelFigure 5-3. Connectors and Leds on front panelLED DescriptionsCPU_LED1: Board user-programmable green

Chapter 5: Connectors and Front Panel4538 Hardware Reference Manual 97Ethernet 10/100 RJ45 Connector J3Table 5-1. RJ48 Connectors J1 and J2Signal,1

List of Figuresvi Interphase Corporation

PMC Connectors98 Interphase CorporationTTY Serial Port J4A 2.5mm stereo jack connector provides a connection to an asynchronous serial device such as

Chapter 5: Connectors and Front Panel4538 Hardware Reference Manual 99 1RWFRQQHFWHG 1RWFRQQHFWHG *1' 6XSSO\ *URXQG 1RWFRQQHFWHG 3

PMC Connectors100 Interphase Corporation 1RWFRQQHFWHG 1RWFRQQHFWHG 3$5 7ULVWDWHELGLUHFWLRQDO 3&,3DULW\ *1' 6XSSO\ *URXQG 9

Chapter 5: Connectors and Front Panel4538 Hardware Reference Manual 101 3&,7', ,QSXW -7$*7HVW,QSXW%HFDXVHWKHERDUGGRHVQRWVXSSRUWWKH

PMC Connectors102 Interphase Corporation 3$' 7ULVWDWHELGLUHFWLRQDO 3&,$GGUHVV'DWD &%( 7ULVWDWHELGLUHFWLRQDO 3&,%

Chapter 5: Connectors and Front Panel4538 Hardware Reference Manual 103PMC Connector P4PMC connector P4 supports the four E1/T1 lines and two TDM buss

PMC Connectors104 Interphase Corporation 1RWFRQQHFWHG 1RWFRQQHFWHG 1RWFRQQHFWHG 1RWFRQQHFWHG 1RWFRQQHFWHG 1RWFRQQHFWHG 1RWF

Chapter 5: Connectors and Front Panel4538 Hardware Reference Manual 105Debug Port J5On the 4538, a 2x8-pin connector can be implemented to provide acc

ISP Enable Jumper JP1106 Interphase CorporationWARNINGJ5 Debug Connector is not compliant to PMC component height specification. It should be removed

Chapter 5: Connectors and Front Panel4538 Hardware Reference Manual 107Connector SummaryCarrier Card SpecificationCompactPCI Carrier CardInterphase ha

4538 Hardware Reference Manual viiList of TablesTable 1-1. PCI Local Space Mapping ...

Carrier Card Specification108 Interphase CorporationJ3 Columns 15 to 19 are unused.J5 Columns 14 to 19 are unused. 30&,2 30&,2 30&

Chapter 5: Connectors and Front Panel4538 Hardware Reference Manual 109Signals printed in bold in Table 5-8 and Table 5-9 shall be routed to the corre

6435 Rear Transition Module110 Interphase Corporation6435 Rear Transition ModuleFigure 5-6. 8-Port 6435 Rear Transition Module Layout

Chapter 5: Connectors and Front Panel4538 Hardware Reference Manual 111NOTEPMC site 1 (J14) corresponds to lines 5 to 8, PMC site 2 (J24) corresponds

6435 Rear Transition Module112 Interphase Corporation

A4538 Hardware Reference Manual 113AMechanical InformationPMC Card Dimensions

Carrier Card Dimension Requirements114 Interphase CorporationCarrier Card Dimension Requirements.H\3RVLWLRQIRU

4538 Hardware Reference Manual 115BibliographyIndustry StandardsEIA-232-D: Interface Between Data Terminal Equipment and Data Circuit-TerminatingEquip

116 Interphase CorporationPICMG 2.0 CompactPCI SpecificationPICMG 2.5 CompactPCI Computer Telephony SpecificationPICMG 2.1 CompactPCI Hot Swap Specifi

4538 Hardware Reference Manual 117ANSI T1.107-1995: Digital Hierarchy - Formats Specifications.ANSI T1.646-1995: Broadband ISDN - Physical Layer Speci

List of Tablesviii Interphase CorporationTable 5-3. J4 TTY Serial Connector ...

118 Interphase Corporation1 specification and test principles.ETSI ETS 300 166 - Transmission and Multiplexing (TM); Physical and electrical character

4538 Hardware Reference Manual 119Infineon PEB22554 / QuadFALC T1/E1/J1 framer4XDG)UDPLQJDQG/LQH,QWHUIDFH&RPSRQHQWIRU(7-4XDG)$/&am

120 Interphase Corporation

4538 Hardware Reference Manual 121GlossaryAAL ATM Adaptation Layer Service-dependent sublayer of the data link layer. The AAL accepts data from differ

Glossary122 Interphase CorporationBRI Basic Rate Interface ISDN interface composed of two B Channels and one D Channel for circuit-switched communicat

Glossary4538 Hardware Reference Manual 123DSX1 Cross-connection point for DS1 signals.DTE Data Terminal Equipment Device at the user end of a user-net

Glossary124 Interphase CorporationITU-T International Telecommunication Union Telecommunication Standardization Sector Interna-tional body that develo

Glossary4538 Hardware Reference Manual 125PDU Protocol Data Unit A message of a given protocol comprising payload and protocol-specific control inform

Glossary126 Interphase CorporationSTS Synchronous Transport SignalSTS1 Synchronous Transport Signal level 1 Basic building block signal of SONET, oper

When using this index, keep in mind that a page number indicates only where referenced material begins.It may extend to the page or pages following th

4538 Hardware Reference Manual ixList of Examples([DPSOH 3RZHU6SDQ,QWHUUXSW0DS5HJLVWHUV,QLWLDOL]DWLRQ&RGH 

List of Examplesx Interphase Corporation

4538 Hardware Reference Manual xiUsing This GuidePurposeThis 4538 Hardware Reference Manual is designed for software developers in Interphase customer

Byte Ordering and Bit Coding Conventionxii Interphase CorporationByte Ordering and Bit Coding ConventionThe PCI bus uses the Little Endian Byte orderi

4538 Hardware Reference Manual xiiiCAUTIONThe Caution icon brings to your attention those items or steps that, if not properly followed, could cause p

Checking and Downloading from the Interphase WWW/FTP Sitexiv Interphase CorporationChecking and Downloading from theInterphase WWW/FTP SiteThe latest

4538 Hardware Reference Manual xvoperating system subdirectories. In these cases, you must choose the proper bus and operating system by typing cd <

Checking and Downloading from the Interphase WWW/FTP Sitexvi Interphase Corporation

14538 Hardware Reference Manual 11Hardware DescriptionOverviewThe Interphase 4538 PMC E1/T1/J1 Communications Controller is a network interface PCI Me

The PowerQUICC II2 Interphase Corporation4538 Hardware StructureFigure 1-1 shows the 4538 hardware structure:Figure 1-1. 4538 StructureThe PowerQUICC

Chapter 1: Hardware Description4538 Hardware Reference Manual 3• Three Fast Serial Communications Controllers (FCCs). One is used to control the Ethe

The PowerQUICC II4 Interphase CorporationOnce all the resets are de-asserted, the PowerQUICC II boots using its 8-bit FLASH device.The MPC8260 can con

Chapter 1: Hardware Description4538 Hardware Reference Manual 5local processor can also be cachable. The peripherals cannot be cachable. The area of S

The PowerQUICC II6 Interphase CorporationFigure 1-2. Local Space Mapping0xF002 00000x0000 00000x8000 00000xC000 00000xCFFF FFFF0xF000 00000xFFFF FFFF

Chapter 1: Hardware Description4538 Hardware Reference Manual 7NOTEAccesses from the CPM and the PowerSpan cannot go through the Memory Management Uni

Copyright Notice© 2001 by Interphase Corporation. All rights reserved.Printed in the United States of America, 2001.This manual is licensed by Interph

The PowerQUICC II8 Interphase CorporationCommunication Processor Module (CPM) I/O PortsThe CPM part of the PowerQUICC II provides several communicatio

Chapter 1: Hardware Description4538 Hardware Reference Manual 97DEOHCPM Port C Usage&30,23RUW 3LQ&RQILJXUDWLRQ 'LU 8VDJH3&

The PowerQUICC II10 Interphase CorporationCAUTIONThe I/O ports described as “Unused” in the tables above must be configured as general purpose outputs

Chapter 1: Hardware Description4538 Hardware Reference Manual 11The two first TDM busses of each serial interface are connected to the four TDM busses

The PowerQUICC II12 Interphase CorporationThree Ethernet LEDs, LED3, LED4, and LED5, driven respectively by the LXT971A LED/CFG(1:3) outputs, are prov

Chapter 1: Hardware Description4538 Hardware Reference Manual 13Figure 1-3. Board CPU_LEDsThe PCI Bridge A dedicated PCI bridge, the Tundra PowerSpan

The PCI Bridge14 Interphase CorporationThe PowerSpan internal register set can be split into six different functional groups:• PCI configuration regi

Chapter 1: Hardware Description4538 Hardware Reference Manual 15These registers are initialized with fixed reset values or with values stored in the I

The PCI Bridge16 Interphase CorporationPowerSpan Processor Bus RegistersThese registers are used to define the parameters of the local to PCI windows.

Chapter 1: Hardware Description4538 Hardware Reference Manual 17PowerSpan DMA RegistersThese registers are used to control the four bidirectional DMA

AssistanceProduct Purchased from ResellerContact the reseller or distributor if• You need ordering, service or any technical assistance.• You receiv

The PCI Bridge18 Interphase CorporationPowerSpan Miscellaneous RegistersThis group of registers includes several configuration registers for the inter

Chapter 1: Hardware Description4538 Hardware Reference Manual 19PowerSpan I²O RegistersThe PowerSpan includes I²O messaging queues controlled by sever

The PCI Bridge20 Interphase CorporationInterrupt pins –INT1 to –INT4 are configured as output ports and conventionally associated with doorbell bits D

Chapter 1: Hardware Description4538 Hardware Reference Manual 21Local to PCI Interrupt (–INTA)The PowerQUICC II can generate an interrupt toward the P

The PCI Bridge22 Interphase CorporationNOTEA PowerSpan PCI-to-Local window must have been enabled in the I²C serial EEPROM, in order to allow the Comp

Chapter 1: Hardware Description4538 Hardware Reference Manual 23Figure 1-4. Local Space Access From PCI Memory SpaceWhen the processor is running, th

The PCI Bridge24 Interphase Corporationdual port RAM, the QuadFALC framers, and the IMA device. (the processor must have its chip selects programmed).

Chapter 1: Hardware Description4538 Hardware Reference Manual 25On the 4538 board, the serial EEPROM content disables the windows. By default, no Loca

The PCI Bridge26 Interphase CorporationFigure 1-5. PCI I/O or Memory Space Access from Local SpaceIn-situ EPLDs ProgrammingSome glue logic is impleme

Chapter 1: Hardware Description4538 Hardware Reference Manual 27These devices keep their programming during power off. So the EPLD should normally be

END-USER LICENSE AGREEMENTFOR INTERPHASE CORPORATION SOFTWAREIMPORTANT NOTICE TO USER–READ CAREFULLYTHIS END-USER LICENSE AGREEMENT FOR INTERPHASE COR

The PCI Bridge28 Interphase CorporationTable 1-24. Hardware Configuration Register Field DescriptionsField DescriptionMPC_ID Microprocessor identifie

Chapter 1: Hardware Description4538 Hardware Reference Manual 29Vital Product Data (VPD)No VPD has been defined for the 4538.Interphase-Specific Produ

The QuadFALC T1/E1/J1 Framer30 Interphase CorporationThe FLASH device is normally controlled by the PowerQUICC II memory controller unit using chip-se

Chapter 1: Hardware Description4538 Hardware Reference Manual 31The QuadFALC includes a flexible clock unit that uses a clock supplied on its MCLK pin

The QuadFALC T1/E1/J1 Framer32 Interphase CorporationFor each line x, the QuadFALC provides four transmit multifunction ports (XPA_x, XPB_x, XPC_x and

Chapter 1: Hardware Description4538 Hardware Reference Manual 33Each line of the QuadFALC framers can be configured independently in Line Termination

TDM Bus Configurations34 Interphase CorporationTDM Bus ConfigurationsGeneralThe TDM bus general structures are described in Figure 1-6 for the general

Chapter 1: Hardware Description4538 Hardware Reference Manual 35Figure 1-6. TDM Busses General Structure5'2B5'2B;',B;',B03&am

TDM Bus Configurations36 Interphase CorporationFigure 1-7. General Clock Structure (Framer 1 & 2)

Chapter 1: Hardware Description4538 Hardware Reference Manual 37Figure 1-8. General Clock Structure (Framer 3 & 4)

Limitation of Liability: NEITHER INTERPHASE NOR ITS LICENSORS SHALL BE LIABLE FOR ANY GENERAL, INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR OTHER DAMAGES A

TDM Bus Configurations38 Interphase CorporationMultiplex Direct Mode In this mode, PA(7) = SWMODE_N = 1 and PA(0) = COMCLK_N = 1.In multiplex direct m

Chapter 1: Hardware Description4538 Hardware Reference Manual 39NOTETDMb1, TDMc1, TDMd1, TDMa2, TDMb2, TDMc2 and TDMd2 signals are not used and must b

TDM Bus Configurations40 Interphase CorporationFigure 1-10. Clocks in Multiplex Direct Mode (Framer 1 & 2)

Chapter 1: Hardware Description4538 Hardware Reference Manual 41Figure 1-11. Clocks in Multiplex Direct Mode (Framer 3 & 4)

TDM Bus Configurations42 Interphase CorporationIndependent Direct ModeIn this mode, PA(7) = SWMODE_N = 1 and PA(0) = COMCLK_N = 1.In independent direc

Chapter 1: Hardware Description4538 Hardware Reference Manual 436&/.54XDG)$/&7'0EB/5&/. 0+]GHMLWWHUHG5HFHLYH6\VWHP&

TDM Bus Configurations44 Interphase CorporationNOTES RCLK2, RCLK3 and RCLK4 must be configured as inputs (PC5.CRP=0). XPA1, XPA2, XPA3 and XPA4 sh

Chapter 1: Hardware Description4538 Hardware Reference Manual 45Figure 1-12. TDM Busses in Independent Direct Mode5'2B5'2B;',B;&apo

TDM Bus Configurations46 Interphase CorporationFigure 1-13. Clocks in Independent Direct Mode (Framer 1 & 2)

Chapter 1: Hardware Description4538 Hardware Reference Manual 47Figure 1-14. Clocks in Independent Direct Mode (Framer 3 & 4)

4538 Hardware Reference Manual iContentsList of Figures

TDM Bus Configurations48 Interphase CorporationSwitched ModeIn this mode, PA(7) = SWMODE_N = 0 and PA(0) = COMCLK_N = 1.In switched mode, the QuadFALC

Chapter 1: Hardware Description4538 Hardware Reference Manual 49NOTETDMb1, TDMc1, TDMd1, TDMa2, TDMb2, TDMc2 and TDMd2 signals are not used and must b

TDM Bus Configurations50 Interphase CorporationFigure 1-16. Clocks in Switched Mode (Framer 1 & 2)

Chapter 1: Hardware Description4538 Hardware Reference Manual 51Figure 1-17. Clocks in Switched Mode (Framer 3 & 4)

TDM Bus Configurations52 Interphase CorporationPass-Through ModeIn this mode, PA(7) = SWMODE_N = 1 and PA(0) = COMCLK_N = 0.Pass through is possible f

Chapter 1: Hardware Description4538 Hardware Reference Manual 53NOTEUnused TDM signals must be tristated.)6&4XDG)$/&53$;3$53$;3$5

TDM Bus Configurations54 Interphase CorporationFigure 1-18. TDM Busses in Pass-Through Mode (1->2 & 3->4 Example)5'2B5'2B;&apos

Chapter 1: Hardware Description4538 Hardware Reference Manual 55Figure 1-19. TDM Busses in Pass-Through Mode (2->1 & 4->3 Example)5'2B

TDM Bus Configurations56 Interphase CorporationFigure 1-20. Clocks in Pass-Through Mode (Framer 1 & 2)

Chapter 1: Hardware Description4538 Hardware Reference Manual 57Figure 1-21. Clocks in Pass-Through Mode (Framer 3 & 4)

Contentsii Interphase CorporationPowerSpan I²O Registers

TDM Bus Configurations58 Interphase Corporation

24538 Hardware Reference Manual 5924538 Power-Up InitializationOverviewAfter power-up, the STARTUP code is executed. This code is written entirely in

PowerSpan Initialization60 Interphase Corporation• PWRUP_BOOT=0: The PowerQUICC II boots locally (not through PCI)• PWRUP_DEBUG_EN=0:Disable debug m

Chapter 2: 4538 Power-Up Initialization4538 Hardware Reference Manual 61Other PowerSpan InitializationsIt is necessary to initialize the PowerSpan Int

PowerQUICC II Hardware Configuration Word62 Interphase CorporationExample 2-1. PowerSpan Interrupt Map Registers Initialization CodePowerQUICC II Har

Chapter 2: 4538 Power-Up Initialization4538 Hardware Reference Manual 63• MMR =11: External bus requests are masked (PQ2 is the boot master)• LBPC =

PowerQUICC II Initializations64 Interphase Corporation• LETM = 1: Enable Local Extended Transfer Mode• NPQM = 111: Non PowerQUICC II master connecte

Chapter 2: 4538 Power-Up Initialization4538 Hardware Reference Manual 65• APPC = 00: Address Parity pins used as local bus• CS10PC = 01:–CS10/–BCTL1

PowerQUICC II Initializations66 Interphase Corporation• Refresh the SDRAM eight times (OP=001)• Write the SDRAM Mode register (OP=011). For the main

Chapter 2: 4538 Power-Up Initialization4538 Hardware Reference Manual 67The instruction and data caches are enabled through bits ICE and DCE of regist

Contents4538 Hardware Reference Manual iiiCPM RCCR Reset 

PowerQUICC II Initializations68 Interphase Corporation

34538 Hardware Reference Manual 693Programming the PeripheralsOverviewThis chapter provides information specific to the 4538 board for peripheral prog

PowerQUICC II CPM Initialization70 Interphase Corporation• RFSDx = 01: Receive frame sync delay for TDMa. 01 for 1 clock delay.• DSCx = 0: Double sp

Chapter 3: Programming the Peripherals4538 Hardware Reference Manual 71TDM Busses in Pass-Through ModeAccording to the TDM busses configuration (VHH7

PowerQUICC II CPM Initialization72 Interphase CorporationFinal Result of SIxAMR (line 1 to 2 and line 3 to 4) and SIxBMR (line 2 to 1 and line 4 to 3)

Chapter 3: Programming the Peripherals4538 Hardware Reference Manual 73Clocks and Baud-Rate GeneratorsIntroductionThe CPM contains eight independent,

PowerQUICC II CPM Initialization74 Interphase CorporationMCCF1 register initialization:• Group 1 = 00: Group 1 (MCC channels 0-31) is used by TDMa1•

Chapter 3: Programming the Peripherals4538 Hardware Reference Manual 75T1/E1/J1 Framer InitializationIntroductionThis section details the QuadFALC reg

T1/E1/J1 Framer Initialization76 Interphase CorporationMultiplexed Direct ModeIn multiplex direct mode, the four framers have the same rhythm. SWMODE_

Chapter 3: Programming the Peripherals4538 Hardware Reference Manual 77NOTEFor T1/J1 applications, the mapping of the receive 24 line time slots over